The present invention relates to a multiple processor system and, more particularly, to a multiple processor system composed of a plurality of instruction processors, wherein a plurality of processes for data processing are efficiently performed simultaneously with and in parallel to each other with improved throughputs of the processing in an environment where the plurality of instruction processors are operable simultaneously with and in parallel to each other.
In order to improve throughputs of data processing in correspondence with an increasing need for data processing, computer systems have been developed from a data processing system in which the data processing is performed with a single instruction processor to a larger-scale multiple processor system composed of a plurality of instruction processors. Such a multiple processor system is provided with a plurality of instruction processors in such a manner that they are operable simultaneously with and in parallel to each other.
In the multiple processor environment composed of a plurality of instruction processors, unlike a single processor environment, a conflict may occur among resources including a memory shared between istruction processors in executing the processing. Once a conflict between resources occurs, the queue time of the resource required by the processors may become longer so that the full capability of each processor cannot be employed to a sufficient extent. Therefore, a processing operation is required which can minimize conflict between resources in order to take advantage of the ability of the processor to its full extent in the multiple processor environment.
In order to achieve a desired throughput in a multiple processor environment with conflict between resources being avoided in executing a plurality of data processings simultaneously and in parallel to each other, conventional operation methods for control of the data processing may be carried out by a processing control, for example, by methods such as:
(1) a method of dynamically determining the relation of a plurality of instruction processors to a plurality of data processings on the basis of the buoy or idle state of an instruction processor (processing in a unit of a task or process); and
(2) a method of executing a particular data processing with a particular instruction processor (processing in a unit of a job).
It is to be noted, however, that these two data processing methods have paid no attention to conflict between resources which are used in common by each instruction processor such as a memory in executing a plurality of data processings simultaneously and in parallel to each other in a multiple processor environment in which a plurality of instruction processors are provided. Therefore, these methods cannot take advantage of the full ability of the multiple processors. More specifically, when input-output resources such as terminal equipment and a magnetic tape unit are shared in performing a plurality of data processings, these conventional data processing methods also share data in a memory such as a buffer memory or a table memory required for input and output so that conflict for use of the memory may be likely to occur between the plural instruction processors, thereby failing to improve the throughputs of the processing.